Apparatuses and methods for compute components formed over an array of memory cells

ABSTRACT

The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. The array can include a plurality of access transistors comprising a first semiconductor material. A compute component can be formed over and coupled to the array. The compute component can include a plurality of compute transistors comprising a second semiconductor material. The second semiconductor material can have a higher concentration of doping ions than the first semiconductor material.

PRIORITY INFORMATION

This application claims the benefit of U.S. Provisional Application No.62/419,004, filed Nov. 8, 2017, the contents of which are includedherein by reference.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor memory andmethods, and more particularly, to apparatuses and methods related tocompute components formed over an array of memory cells.

BACKGROUND

Memory devices are typically provided as internal, semiconductor,integrated circuits in computing systems. There are many different typesof memory including volatile and non-volatile memory. Volatile memorycan require power to maintain its data (e.g., host data, error data,etc.) and includes random access memory (RAM), dynamic random accessmemory (DRAM), static random access memory (SRAM), synchronous dynamicrandom access memory (SDRAM), and thyristor random access memory (TRAM),among others. Non-volatile memory can provide persistent data byretaining stored data when not powered and can include NAND flashmemory, NOR flash memory, and resistance variable memory such as phasechange random access memory (PCRAM), resistive random access memory(RRAM), and magnetoresistive random access memory (MRAM), such as spintorque transfer random access memory (STT RAM), among others.

Computing systems often include a number of processing resources (e.g.,one or more processors), which may retrieve and execute instructions andstore the results of the executed instructions to a suitable location. Aprocessing resource can comprise a number of functional units such asarithmetic logic unit (ALU) circuitry, floating point unit (FPU)circuitry, and a combinatorial logic block, for example, which can beused to execute instructions by performing logical operations such asAND, OR, NOT, NAND, NOR, and XOR, and invert (e.g., inversion) logicaloperations on data (e.g., one or more operands). For example, functionalunit circuitry may be used to perform arithmetic operations such asaddition, subtraction, multiplication, and division on operands via anumber of logical operations.

A number of components in a computing system may be involved inproviding instructions to the functional unit circuitry for execution.The instructions may be executed, for instance, by a processing resourcesuch as a controller and/or host processor. Data (e.g., the operands onwhich the instructions will be executed) may be stored in a memory arraythat is accessible by the functional unit circuitry. The instructionsand data may be retrieved from the memory array and sequenced and/orbuffered before the functional unit circuitry begins to executeinstructions on the data. Furthermore, as different types of operationsmay be executed in one or multiple clock cycles through the functionalunit circuitry, intermediate results of the instructions and data mayalso be sequenced and/or buffered.

In many instances, the processing resources (e.g., processor and/orassociated functional unit circuitry) may be external to the memoryarray, and data is accessed via a bus between the processing resourcesand the memory array to execute a set of instructions. Processingperformance may be improved in an in-memory intelligence (IMI) device,which can also be referred to as a processing-in-memory (PIM) device, inwhich a processing resource may be implemented internal and/or near to amemory (e.g., directly on a same chip as the memory array). An IMIdevice may reduce time in processing and may also conserve power. Datamovement between and within arrays and/or subarrays of various memorydevices, such as IMI devices, can affect processing time and/or powerconsumption.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an apparatus in the form of a computingsystem including a memory device in accordance with a number ofembodiments of the present disclosure.

FIG. 2 is a block diagram illustrating a cross-sectional view of aportion of a memory device in accordance with a number of embodiments ofthe present disclosure.

FIG. 3 is a schematic diagram illustrating a cross-sectional view of aportion of a memory device in accordance with a number of embodiments ofthe present disclosure.

FIG. 4 is a schematic diagram illustrating a cross-sectional view of aportion of a memory device comprising layered memory tiers in accordancewith a number of embodiments of the present disclosure.

FIG. 5 is a schematic diagram illustrating sensing circuitry inaccordance with a number of embodiments of the present disclosure.

FIG. 6 is a logic table illustrating selectable logic operation resultsimplemented by sensing circuitry in accordance with a number ofembodiments of the present disclosure.

DETAILED DESCRIPTION

The present disclosure includes apparatuses and methods related tocompute components formed over an array of memory cells. An exampleapparatus comprises a base substrate material and an array of memorycells formed over the base substrate material. The array can include aplurality of access transistors comprising a first semiconductormaterial. The compute component can be formed over and coupled to thearray. The compute component can include a plurality of computetransistors comprising a second semiconductor material. Sensingcircuitry can be formed over and coupled to the array, wherein thesensing circuitry comprises the compute component and a sense amplifiercoupled to the compute component. The second semiconductor material canhave a higher concentration of doping ions than the first semiconductormaterial. The second semiconductor material having a higherconcentration of doping ions than the first semiconductor material canbe done as part of optimizing leakage characteristics of transistors,such as access transistors, for a low leakage current.

In some approaches, memory devices may comprise an array of memory cellsformed on a base substrate material. A memory device may be formed fromthe bottom up, starting with the base substrate material. Accesstransistors and sensing circuitry may be formed in the base substratematerial. However, forming the array of memory cells may require severalheating cycles. These heating cycles affect the concentration of dopingions in semiconductor components formed prior to the heating cycles bylowering the concentration of doping ions.

Doping ions in a semiconductor material formed prior to the heatingcycles needed to form a storage element (e.g., a memory cell) can moveduring the heating cycles such that the ions disperse in the substrate,forming leakage paths. Thus, a semiconductor component that was heavilydoped so as to have a high concentration of doping ions may end uphaving significant leakage paths as a result of the subsequent heatingcycles. While, a lower concentration of doping ions may result in slowertransistors as a function of increased resistance, it also may result inlower leakage currents. Lower leakage currents for access transistors(e.g., DRAM access transistors) may enhance DRAM data retention time.These lower leakage currents can help preserve charge stored in astorage element coupled to an access transistor from leaking array fromthe storage element. If charge leaks out then a data value stored in thestorage element can changed over time. Consequently, it can bebeneficial to have the base substrate material and the accesstransistors of a memory device to have a low concentration of dopingions. Therefore, access transistors that are formed in the basesubstrate material can be formed having an initial low concentration ofdoping ions.

An IMI device can comprise a compute component, which can comprise aplurality of compute transistors used in performing computations on datastored in the array. The compute component can benefit from being formedof a semiconductor material having a higher concentration of dopingions. Doping a semiconductor material to a high concentration of dopingions causes the semiconductor material to become a better conductor ofelectricity. As a better conductor of electricity, transistors formed inthe material having a high concentration of doping ions can switchfaster and have shorter switching times than the other semiconductorcomponents, such as access transistors formed in a semiconductormaterial having a low concentration of doping ions.

Because the compute component can comprise transistors (e.g., aplurality of compute transistors) used to perform computations, viaperforming logic operations, it can be beneficial to form transistors ofthe compute component having a high concentration of doping ions. Asemiconductor material having a high concentration of doping ions canhave a high leakage current. If components other than the computecomponent, such as access transistors, have a high leakage current, thenthe memory cell retention time for those components can be shortened. Asused herein, “memory cell retention time” refers to the time which amemory cell is able to hold a charge, which can correspond to data, suchthat when the memory cell is read (e.g., by a sense amplifier) the datais interpreted correctly. Because transistors of the compute componentare not used for data storage, a higher leakage current is notproblematic, but rather beneficial because of the shorter switchingtimes. In an IMI device that includes an array of storage elements wherethe storage elements formed over each other (e.g., layered), the heatingcycles can compound the dispersal of doping ions of semiconductorcomponents formed before the storage elements, further exasperating thetradeoffs between fast switching transistors for logic transistors andlow-leaking transistors for storage (e.g., DRAM storage).

At least one embodiment of the present disclosure can include a memorydevice being a multi-layer memory device. In a multi-layer memory devicewhere multiple semiconductor materials are formed on top of each other(e.g., a layered formation), semiconductor materials formed before(e.g., lower layers) other semiconductor materials (e.g., upper layers)can be subjected to more heating cycles than the other semiconductormaterials (e.g., the upper layers). A lowered concentration of dopingmay negatively affect the performance of the compute transistors, andconsequently the performance of the IMI device. Thus, it can bebeneficial to form semiconductor materials having a high concentrationof doping ions after forming the lower layers (e.g., as an uppermostlayer(s)) such that the high concentration of doping ions in theuppermost layer(s) can be maintained. Thus, it can be beneficial to formthe compute component after an array of storage elements has beenformed.

By forming compute circuitry in a semiconductor material formed over anarray of storage elements, the compute component in the semiconductormaterial is not subjected to the heating cycles from forming the arrayof storage elements. Thus, a greater level of control of theconcentration of doping ions in the semiconductor material can beachieved such that the concentration of doping ions of the semiconductormaterial can be maintained.

In the following detailed description of the present disclosure,reference is made to the accompanying drawings that form a part hereof,and in which is shown by way of illustration how one or more embodimentsof the disclosure may be practiced. These embodiments are described insufficient detail to enable those of ordinary skill in the art topractice the embodiments of this disclosure, and it is to be understoodthat other embodiments may be utilized and that process, electrical,and/or structural changes may be made without departing from the scopeof the present disclosure. As used herein, designators such as “n”,particularly with respect to reference numerals in the drawings,indicate that a number of the particular feature so designated can beincluded. As used herein, “a number of” a particular thing refers to oneor more of such things (e.g., a number of memory arrays can refer to oneor more memory arrays). A “plurality of” is intended to refer to morethan one of such things.

The figures herein follow a numbering convention in which the firstdigit or digits correspond to the drawing figure number and theremaining digits identify an element or component in the drawing.Similar elements or components between different figures may beidentified by the use of similar digits. For example, 215 may referenceelement “15” in FIG. 2, and a similar element may be referenced as 315in FIG. 3. As will be appreciated, elements shown in the variousembodiments herein can be added, exchanged, and/or eliminated so as toprovide a number of additional embodiments of the present disclosure. Inaddition, as will be appreciated, the proportion and the relative scaleof the elements provided in the figures are intended to illustratecertain embodiments of the present invention, and should not be taken ina limiting sense.

FIG. 1 is a block diagram of an apparatus in the form of a computingsystem 100 including a memory device 102 in accordance with a number ofembodiments of the present disclosure. As used herein, a memory device102, a controller 103, a memory array 110, and/or sensing circuitry 106might also be separately considered an “apparatus.”

The system 100 includes a host 101 coupled (e.g., connected) to thememory device 102, which includes a memory array 110. The host 101 canbe a host system such as a personal laptop computer, a desktop computer,a digital camera, a smart phone, or a memory card reader, among variousother types of hosts. The host 101 can include a system motherboardand/or backplane and can include a number of processing resources (e.g.,one or more processors, microprocessors, or some other type ofcontrolling circuitry). The system 100 can include separate integratedcircuits or both the host 101 and the memory device 102 can be on thesame integrated circuit. The system 100 can be, for instance, a serversystem and/or a high performance computing (HPC) system and/or a portionthereof. Although the example shown in FIG. 1 illustrates a systemhaving a Von Neumann architecture, embodiments of the present disclosurecan be implemented in non-Von Neumann architectures, which may notinclude one or more components (e.g., CPU, ALU, etc.) often associatedwith a Von Neumann architecture.

For clarity, the system 100 has been simplified to focus on featureswith particular relevance to the present disclosure. The memory array110 can be a hybrid memory cube (HMC), computational memory such as aprocessing-in-memory random access memory (PIMRAM) array, which caninclude one or more of a DRAM array, SRAM array, STT RAM array, PCRAMarray, TRAM array, RRAM array, NAND flash array, and/or NOR flash array,for instance. The memory array 110 can comprise memory cells arranged inrows coupled by access lines, which may be referred to herein as wordlines or select lines, and columns coupled by digit lines, which may bereferred to herein as bit lines, data lines, or sense lines. Although asingle memory array 110 is shown in FIG. 1, embodiments are not solimited. For instance, the memory device 102 may include a number ofmemory arrays 110 (e.g., a number of banks of DRAM cells, NAND flashcells, etc.).

The memory device 102 can include address circuitry 104 to latch addresssignals for data provided over an input/output “I/O” bus 172 (e.g., databus and/or address bus) through I/O circuitry 109 (e.g., provided toexternal ALU circuitry and to DRAM DQs via local I/O lines and globalI/O lines). Address signals are received through address circuitry 104and decoded by a row decoder 105 and a column decoder 107 to access thememory array 110. Data can be read from the memory array 110 by sensingvoltage and/or current changes on the digit lines using the sensingcircuitry 106. The sensing circuitry 106 can read and latch a page(e.g., row) of data from the memory array 110. The I/O circuitry 109 canbe used for bi-directional data communication with the host 101 over theI/O bus 172. In a number of embodiments, sensing circuitry 106 caninclude a number of sense amplifiers and a respective number of computecomponents as will be discussed further herein. The write circuitry 108can be used to write data to the memory array 110.

The controller 103 (e.g., memory controller) decodes signals provided bythe control bus 170 from the host 101. These signals can include chipenable signals, write enable signals, and address latch signals that areused to control operations performed on the memory array 110, includingdata read, data write, and data erase operations. In variousembodiments, the controller 103 is responsible for executinginstructions from the host 101 and sequencing access to the memory array110. The controller 103 can be a state machine, sequencer, or some othertype of controller, and include hardware and/or firmware (e.g.,microcode instructions) in the form of an application specificintegrated circuit (ASIC). The controller 103 can control, for example,generation of clock signals and application of the clock signals to acompute component in sensing circuitry in association with shifting datain accordance with embodiments described herein.

In a number of embodiments, the sensing circuitry 106 can comprise asense amplifier and a compute component. The compute component may alsobe referred to herein as an accumulator, and can be used to performlogical operations (e.g., on data associated with a pair ofcomplementary digit lines). The compute component can comprise aplurality of transistors, which can be referred to as computetransistors. According to various embodiments, the compute componentcomprises a first storage location and a second storage location. Thefirst and second storage locations of the sensing components can serveas stages of a shift register. For example, clock signals can be appliedto the sensing components to move data values between the first andsecond storage locations and to shift data between adjacent sensingcomponents.

In a number of embodiments, the sensing circuitry 106 can be used toperform logical operations using data stored in the memory array 110 asinputs and/or store the results of the logical operations back to thememory array 110 without transferring data via a digit line addressaccess (e.g., without firing a column decode signal). As such, variouscompute functions can be performed using, and within, the sensingcircuitry 106 rather than (or in association with) being performed byprocessing resources external to the sensing circuitry 106 (e.g., by aprocessing resource associated with the host 101 and/or other processingcircuitry, such as ALU circuitry, located on device 102 (e.g., on thecontroller 103 or elsewhere)).

In various previous approaches, data associated with an operand, forinstance, would be read from memory via sensing circuitry and providedto external ALU circuitry via I/O lines (e.g., via local I/O linesand/or global I/O lines). The external ALU circuitry could include anumber of registers and would perform compute functions using theoperands, and the result would be transferred back to the array via theI/O lines. In contrast, in a number of embodiments of the presentdisclosure, the sensing circuitry 106 is configured to perform logicaloperations on data stored in the memory array 110 and store the resultback to the memory array 110 without enabling an I/O line (e.g., a localI/O line) coupled to the sensing circuitry 106.

As such, in a number of embodiments, circuitry external to the memoryarray 110 and sensing circuitry 106 is not needed to perform computefunctions as the sensing circuitry 106 can perform the appropriatelogical operations to perform such compute functions without the use ofan external processing resource. Therefore, the sensing circuitry 106may be used to complement and/or to replace, at least to some extent,such an external processing resource (or at least the bandwidthconsumption of such an external processing resource).

However, in a number of embodiments, the sensing circuitry 106 may beused to perform logical operations (e.g., to execute instructions) inaddition to logical operations performed by an external processingresource (e.g., the host 101). For instance, the host 101 and/or sensingcircuitry 106 may be limited to performing only certain logicaloperations and/or a certain number of logical operations.

In a number of embodiments, the sensing circuitry 106 can be formed on asame pitch as a pair of complementary sense lines of the array. Forexample, the cells of a memory array may have a 4F² or 6F² cell size,where “F” is a feature size corresponding to the cells. As an example, apair of complementary memory cells may have a cell size with a 6F² pitch(e.g., 3F×2F). If the pitch of a pair of complementary sense lines forthe complementary memory cells is 3F, then the sensing circuitry beingon pitch indicates the sensing circuitry (e.g., a sense amplifier andcorresponding compute component per respective pair of complementarysense lines) is formed to fit within the 3F pitch of the complementarysense lines.

Enabling an I/O line can include enabling (e.g., turning on) atransistor having a gate coupled to a decode signal (e.g., a columndecode signal) and a source/drain coupled to the I/O line. However,embodiments are not limited to performing logical operations usingsensing circuitry (e.g., the sensing circuitry 106) without enablingcolumn decode lines of the memory array 110. Whether or not local I/Olines are used in association with performing logical operations viasensing circuitry 106, the local I/O line(s) may be enabled in order totransfer a result to a suitable location other than back to the memoryarray 110 (e.g., to an external register).

FIG. 2 is a block diagram illustrating a cross-sectional view of aportion of a memory device 202 in accordance with a number ofembodiments of the present disclosure. For illustration purposes only, aset of axes 211 are used to show the orientation of a cross-sectionalview of the portion of a multi-layer memory device 202. The x-directionfollows the width of the page and the z-direction follows the length ofthe page. The y-direction (not shown) is into and out of the page. Thememory device 202 can be analogous to the memory device 102 illustratedin FIG. 1. In the embodiment of FIG. 2, the memory device 202 is amulti-layer memory device. The memory device 202 can comprise a basesubstrate material 215, a first semiconductor material 262 formed overthe base substrate material 215, and a second semiconductor material 264formed over the first semiconductor material 262. The base substratematerial 215 can be a monocrystalline silicon base substrate. The firstsemiconductor material 262 can be an amorphous silicon firstsemiconductor material. The second semiconductor material 264 can be anamorphous silicon second semiconductor material. Although FIG. 2 showstwo semiconductor materials, the first semiconductor material 262 andthe second semiconductor material 264, any number of semiconductormaterials can be formed over the base substrate material 215. Forexample, a third semiconductor material (not shown) can be formed overthe second semiconductor material 264, a fourth semiconductor material(not shown) can be formed over the third semiconductor material, and soon.

A plurality of access transistors can be formed in the base substratematerial 215 or formed over the base substrate material 215 such thatthe plurality of access transistors comprises the first semiconductormaterial 262. The plurality of access transistors can be coupled to anarray of storage elements formed over the base substrate material 215.In at least one embodiment in accordance with the present disclosure,the array of storage elements can include the plurality of accesstransistors directly coupled to the storage elements such that thestorage elements and the plurality of access transistors togethercomprise an array of memory cells (e.g., a DRAM array). Examples ofarrays of memory cells in accordance with the present disclosure areillustrated in FIGS. 3 and 4.

A compute component (not shown), which can comprise a plurality ofcompute transistors, can be formed over the array of storage elementssuch that the plurality of compute transistors comprises the secondsemiconductor material 264. The memory device 202 can comprise aplurality of metal interconnects (not shown) that interconnects, theplurality of access transistors, the array of storage elements, and thecompute component.

In at least one embodiment in accordance with the present disclosure, afirst portion of the sensing circuitry (e.g., a sense amplifier) can beformed in the base substrate material 215 and a second portion of thesensing circuitry (e.g., at least a portion of the compute component)can be formed over the array of storage elements. For example, aplurality of sense amplifiers can be formed in the base substratematerial 215 as part of the first portion of the sensing circuitry and aplurality of compute transistors of the compute component comprising thesecond semiconductor material 264 can be formed over the array ofstorage elements as part of the second portion of the sensing circuitry.

The second semiconductor material 264 can be doped to a higher dopingconcentration than the first semiconductor material 262 or the basesubstrate material 215. A higher concentration of doping ions candecrease the leakage current. As discussed above, high leakage currentscan hinder the performance of a memory array because memory cellretention times can be diminished. However, a lower concentration ofdoping ions can correspond to shorter refresh intervals. For example,compute transistors formed of the second semiconductor material 264having a low concentration of doping ions can have shorter refreshintervals than access transistors formed of the first semiconductormaterial 262 or the base substrate material 215 having a highconcentration of doping ions. Faster switching can be a function of ashorter refresh cycle time. Access transistors having short refreshintervals can be detrimental to the performance of a memory array.

FIG. 3 is a schematic diagram illustrating a cross-sectional view of aportion of a memory device 302 in accordance with a number ofembodiments of the present disclosure. For illustration purposes only, aset of axes 311 are used to show the orientation of a cross-sectionalview of the memory array 310. The x-direction follows the width of thepage and the z-direction follows the length of the page. The y-direction(not shown) is into and out of the page. The memory device 302 can beanalogous to the memory device 102 illustrated in FIG. 1. The memoryarray 310 can be analogous to the memory array 110 illustrated inFIG. 1. The base substrate material 315 can be analogous to the basesubstrate material 215 illustrated in FIG. 2.

FIG. 3 illustrates a portion of an array of memory cells comprising twotransistor-one capacitor (2T-1C) memory cells. Specifically, a pair ofadjacent memory cells 312 and 312 a are illustrated. A box 313demarcates an approximate boundary of the memory cell 312. The memorycells 312 and 312 a can be substantially identical to one another, withthe term “substantially identical” meaning that the memory cells areidentical to within reasonable tolerances of fabrication andmeasurement.

The illustrated portion of the array of memory cells is supported by abase substrate material 315. The base substrate material 315 cancomprise a semiconductor material; and can, for example, comprise,consist essentially of, or consist of monocrystalline silicon. The basesubstrate material 315 may be referred to as a semiconductor substrate.The term “semiconductor substrate” means any construction comprisingsemiconductive material, including, but not limited to, bulksemiconductive materials such as a semiconductive wafer (either alone orin assemblies comprising other materials), and semiconductive materiallayers (either alone or in assemblies comprising other materials). Theterm “substrate” refers to any supporting structure, including, but notlimited to, the semiconductor substrates described above. In someembodiments, the base substrate material 315 can correspond to asemiconductor substrate containing one or more materials associated withintegrated circuit fabrication. Such materials can include, for example,one or more of refractory metal materials, barrier materials, diffusionmaterials, insulator materials, etc.

The base substrate material 315 is shown to be spaced from components ofthe memory array 310 to indicate that other circuitry or components maybe between the memory cells 312 and 312 a and the base substratematerial 315. For example, additional pairs of memory cells 312 and 312a can be formed between the memory cells 312 and 312 a illustrated inFIG. 3 and the base substrate material 315. Although FIG. 3 illustratessensing circuitry 306, which can be analogous to the sensing circuitry106 illustrated in FIG. 1, being located above the memory array 310, aportion of the sensing circuitry 306 can be formed between the memorycells 312 and 312 a and the base substrate material 315. For example,sense amplifiers 380 and 380 a of the sensing circuitry 306 can beformed in the base substrate material 315 such that the computecomponents 382 and 382 a without sense amplifiers 380 and 380 a arelocated above the memory array 310. Although FIG. 3 illustrates thecompute components 382 and 382 a being located above the memory array310, a portion of the compute components 382 and 382 a (e.g., the latch591 illustrated in FIG. 5) can be formed between the memory cells 312and 312 a and the base substrate material 315. An interlayer insulatingfilm 317 can intervene between the base substrate material 315 and thememory array 310. The insulating film 317 can comprise any suitableelectrically insulative material or combination of insulative materials,including, for example, silicon dioxide, silicon nitride, etc.

In the illustrated embodiment, the insulating film 317 has asubstantially planar upper surface, and the comparative digit lines(e.g., bit lines (BL)) BL-1, BL-2, BL-1 a and BL-2 a are disposed onsuch upper surface, and in parallel with one another. The term“substantially planar” means planar to within reasonable tolerances offabrication and measurement.

The memory cell 312 comprises a pair of complementary digit lines BL-1and BL-2, and comprises transistors T1 and T2 over the digit lines BL-1and BL-2, respectively. Similarly the memory cell 312 a comprises a pairof complementary digit lines BL-1 a and BL-2 a, and comprisestransistors T1 a and T2 a. The pair of complementary digit lines BL-1and BL-2 can be coupled to sensing circuitry 306. The sensing circuitry306 can be formed over the memory cells 312 and 312 a. Similarly, thepair of complementary digit lines BL-1 a and BL-2 a can be coupled tothe sensing circuitry 306.

As illustrated in FIG. 3, the complementary pair of digit lines BL-1 andBL-2 of memory cell 312 are laterally displaced relative to one another,and similarly the transistors T1 and T2 are laterally displaced relativeto one another. The transistors T1 and T2 are shown to be in a commonhorizontal plane as one another (i.e., are horizontally aligned with oneanother), but in other embodiments can be vertically offset relative toone another.

The transistors T1 and T2 comprise gates 314 and 316; and similarly thetransistors T1 a and T2 a comprise gates 314 a and 316 a. The memorycells 312 and 312 a are in a common row as one another within the memoryarray, and accordingly a word line (WL) extends across all of thetransistors T1, T1 a, T2 and T2 a, and comprises the gates of thetransistors. The word line and the digit lines can comprise any suitableelectrically conductive material, including, for example, one or more ofvarious metals (e.g., tungsten, titanium, etc.), metal containingcompositions (e.g., metal nitride, metal carbide, metal silicide, etc.),conductively-doped semiconductor materials (e.g., conductively-dopedsilicon, conductively-doped germanium, etc.), etc. The word line anddigit lines may comprise the same composition as one another, or cancomprise different compositions relative to one another.

Semiconductor pillars 318 and 320 extend upwardly from the complementarydigit lines BL-1 and BL-2. Similarly, semiconductor pillars 318 a and320 a extend upwardly from the complementary digit lines BL-1 a and BL-2a. Semiconductor pillars 318, 320, 318 a, and 320 a can comprise anysuitable semiconductor materials including, for example, one or both ofsilicon and germanium.

The semiconductor pillars 318, 320, 318 a and 320 a can comprise a firstsemiconductor material. The first semiconductor material can beanalogous to the first semiconductor material 262 illustrated in FIG. 2.The first semiconductor material can be doped to a first concentrationof doping ions. The first concentration can be such that the transistorsT1, T2, T1 a, and T2 a have a low leakage current. A low leakage currentcan improve data retention because charge stored on the capacitors 338and 338 a may not leak out of the capacitors 338 and 338 a through thecorresponding transistors T1, T2, T1 a, and T2 a. The secondsemiconductor material, in which the compute components 382 and 382 a orthe sensing circuitry 306 can be formed, can be doped to a secondconcentration of doping ions. The second concentration can be higher, orlower, than the first concentration.

The transistor gate 314 is spaced from the semiconductor pillar 318 by agate dielectric material 322, and the transistor gate 316 is spaced fromthe semiconductor pillar 320 by a gate dielectric material 324. The gatedielectric materials 322 and 324 can comprise any suitable compositionsor combinations of compositions, including, for example, silicondioxide, silicon nitride, high-K dielectric material, ferroelectricmaterial, etc. The gate dielectric materials 322 a and 324 a within thetransistors T1 a and T2 a can be analogous to the gate dielectricmaterials 322 and 324.

The transistor T1 comprises a channel region 326 within thesemiconductor pillar 318, and comprises source/drain regions 328 and 330on opposing sides of the channel region. The source/drain regions 328and 330 and the channel region 326 can be doped with any suitable dopingions. In some embodiments, the source/drain regions 328 and 330 can ben-type majority doped, and in other embodiments may be p-type majoritydoped.

The transistor T2 comprises a channel region 332 within thesemiconductor pillar 320, and comprises source/drain regions 334 and 336on opposing sides of the channel region 332. In some embodiments, thesource/drain regions 334 and 336 may be n-type majority doped, and inother embodiments can be p-type majority doped. In some embodiments, thesource/drain regions 328 and 330 can be referred to as first and secondsource/drain regions, respectively; and the source/drain regions 334 and336 can be referred to as third and fourth source/drain regions,respectively.

The transistors T1 a and T2 a comprise source/drain regions 328 a, 330a, 334 a, and 336 a and channel regions 326 a and 332 a, which can beanalogous those described with reference to the transistors T1 and T2.

As shown in FIG. 3, sensing circuitry 306 can comprise a sense amplifier380 coupled to the pair of complementary digit lines BL-1 and BL-2 viametal interconnects 368 and a sense amplifier 380 a coupled to the pairof complementary digit lines BL-1 a and BL-2 a via metal interconnects368 a. The sense amplifiers 380 and 380 a can be coupled to computecomponents 382 and 382 a, respectively. The compute components 382 and382 a can be a discrete collection of elements. For example, the computecomponents 382 and 382 a can comprise a plurality of compute transistors(which can be referred to as “Boolean logic”), an accumulator storagelocation, and a shift storage location. The plurality of computetransistors can comprise a second semiconductor material. The secondsemiconductor material can be analogous to the second semiconductormaterial 264 illustrated in FIG. 2. The second semiconductor materialcan be doped to a second concentration of doping ions. Although notillustrated in FIG. 3, the compute components 382 and 382 a can includeselectable logical operation selection logic.

In some embodiments, the compute components 382 and 382 a can be coupledto another compute component such that data values (e.g., bits) can bemoved (e.g., shifted) from one compute component to another computecomponent. Shifting data values between one compute component andanother compute component may be done synchronously such that a computecomponent receives a data value from another compute component as thecompute component passes its data value to yet another computecomponent. In some embodiments, shifting data in the compute components382 and 382 a can facilitate various processing functions such as themultiplication, addition, etc. of two operands.

The memory cell 312 comprises a capacitor 338 which is verticallydisplaced relative to transistors T1 and T2, and as illustrated in FIG.3, is over the transistors T1 and T2. The capacitor 338 can be a storageelement. The capacitor 338 comprises an outer node (or first node) 340,an inner node (or second node) 342, and a capacitor dielectric material344 between the outer and inner nodes 340 and 342. In the embodiment ofFIG. 3 the outer node 340 is container-shaped, and the inner node 342and the capacitor dielectric material 344 extend into thecontainer-shaped outer node 340. In some embodiments, the outer node 340can have a different configuration (e.g., a planar configuration).

The outer and inner nodes 340 and 342 can comprise any suitableelectrically conductive compositions or combinations of electricallyconductive compositions, including, for example, one or more of variousmetals (e.g., tungsten, titanium, etc.), metal containing materials (forinstance, metal nitride, metal silicide, metal carbide, etc.),conductively-doped semiconductor materials (for instance,conductively-doped silicon, conductively-doped germanium, etc.), etc.The outer and inner nodes 340 and 342 can comprise the same compositionas one another in some embodiments, and in other embodiments cancomprise different compositions relative to one another.

The capacitor dielectric material 344 can comprise any suitablecomposition or combination of compositions. In some embodiments, thecapacitor dielectric material may comprise non-ferroelectric materialand may, for example, consist of one or more of silicon dioxide, siliconnitride, aluminum oxide, hafnium oxide, zirconium oxide, etc. In someembodiments the capacitor dielectric material may comprise ferroelectricmaterial. For instance, the capacitor dielectric material may comprise,consist essentially of, or consist of one or more materials selectedfrom the group consisting of transition metal oxide, zirconium,zirconium oxide, hafnium, hafnium oxide, lead zirconium titanate,tantalum oxide, and barium strontium titanate; and having dopant thereinwhich comprises one or more of silicon, aluminum, lanthanum, yttrium,erbium, calcium, magnesium, niobium, strontium, and a rare earthelement.

As illustrated in FIG. 3, the outer electrode 340 is electricallycoupled with the first source/drain region 328 of transistor T1, and theinner electrode 342 is electrically coupled with the third source/drainregion 334 of transistor T2. The second source/drain region 330 oftransistor T1 is electrically coupled with complementary digit line BL-1and the fourth source/drain region 336 of transistor T2 is electricallycoupled with complementary digit line BL-2. The capacitor 338, togetherwith transistors T1 and T2, and complementary digit lines BL-1 and BL-2,forms a 2T-1C memory cell. The inner electrode 342 is shown having asingle homogenous composition that extends from inside of thecontainer-shaped outer electrode 340 to outside of the container-shapedouter electrode 340 and into electrical contact with the source/drainregion 334. In some embodiments, at least some of the illustratedportion of the inner electrode 342 outside of the container-shaped outerelectrode 340 can be replaced with an electrically conductiveinterconnect which may or may not have a same composition as the innerelectrode 342.

The memory cell 312 a comprises a capacitor 338 a, which can beanalogous to the capacitor 338 of the memory cell 312 (with thecapacitor 338 a comprising a first node 340 a, a second node 342 a, anda capacitor dielectric material 344 a), and also comprises a 2T-1Cmemory cell.

An insulative material 348 is shown to surround the various componentsof memory cells 312 and 312 a. Such insulative material may comprise anysuitable composition or combination of compositions; including, forexample, one or more of silicon dioxide, silicon nitride,borophosphosilicate glass, spin-on dielectric, etc. Although theinsulative material 348 is shown as a single homogeneous material, inother embodiments the insulative material may include two or morediscrete insulative compositions.

Although not illustrated in FIG. 3, the embodiment illustrated in FIG. 3can include global metal interconnects and pads directly coupled to thesensing circuitry 306. A benefit of having the global metalinterconnects and pads directly coupled to the sensing circuitry 306 canbe reduced resistive and capacitive loads on the interface between thememory array 310 and other devices or components coupled to the memoryarray 310 (e.g., transmitting data to and from the memory array 310).The reduction of the resistive and capacitive loads can be a result ofthe shorter distance between the sensing circuitry and the global metalinterconnects and pads.

A controller, such as the controller 103 illustrated in FIG. 1, can becoupled to the memory array 310 and the sensing circuitry 306, forexample, via the global metal interconnects and pads (not shown).Although not illustrated in FIG. 3, in an embodiment where senseamplifiers 380 and 380 a are located elsewhere in the memory device 302,such as being formed in the base substrate material 315, the controllercan be, for example, coupled to the memory array 310 and the computecomponents 382 and 382 a via the global metal interconnects and pads(not shown) and to the sense amplifiers 380 and 380 a via the metalinterconnects 368 and 368 a. The controller can be configured to causedata to be transmitted, via the metal interconnects 368 and 368 a,between the memory cells 312 and 312 a, the sensing circuitry 306, andthe global metal interconnects and pads.

The controller can be directly coupled to the global metal interconnectsand pads (not shown) such that the controller is formed over theuppermost semiconductor material of a multi-layer memory device.Minimizing the distance between the controller and the computetransistors can enhance the benefit of compute components comprising asemiconductor material having a lower concentration of doping ionsformed over a semiconductor material having a lower concentration ofdoping ions.

FIG. 4 is a schematic diagram illustrating a cross-sectional view of aportion of a memory device comprising layered memory tiers 452 and 454in accordance with a number of embodiments of the present disclosure.The memory device 402 can be analogous to the memory device 102illustrated in FIG. 1. The memory array 410 can be analogous to thememory array 110 illustrated in FIG. 1. The base substrate material 415can be analogous to the base substrate material 215 illustrated in FIG.2. The sensing circuitry 406 can be analogous to the sensing circuitry306 illustrated in FIG. 3. The sense amplifiers 480 and 480 a, thecompute components 482 and 482 a, and the metal interconnects 468 and468 a can be analogous to the sense amplifiers 380 and 380 a, thecompute components 382 and 382 a, and the metal interconnects 368 and368 a illustrated in FIG. 3, respectively.

FIG. 4 illustrates an array of memory cells in the form of layeredmemory array tiers. For illustration purposes only, a set of axes 411are used to show the orientation of a cross-sectional view of the memorydevice 402. The x-direction follows the width of the page and thez-direction follows the length of the page. The y-direction (not shown)is into and out of the page. A second memory array tier 454 is formed ona first memory array tier 452. The first memory array tier 452 comprisesmemory cells 412 and 412 a, which can be analogous the memory cells 312and 312 a illustrated in FIG. 3. The second memory array tier 454comprises memory cells 412 b and 412 c that are analogous to the memorycells 412 and 412 a, except that the memory cells 412 b and 412 c areinverted relative to the memory cells 412 and 412 a. The memory cell 412b comprises first and second transistors T1 b and T2 b, and the memorycell 412 c comprises first and second transistors T1 c and T2 c. Thememory cells 412 b and 412 c comprise capacitors 438 b and 438 c,respectively. The word line extending across the memory cells 412 and412 a is labeled as a first word line WL1, and the word line across thememory cells 412 b and 412 c is labeled as a second word line WL2.

The complementary digit lines BL-1 and BL-2 can be coupled to sensingcircuitry 406 formed over the memory cells 412 b and 412 c. AlthoughFIG. 4 illustrates sensing circuitry 406 being located above the memoryarray 410, a portion of the sensing circuitry 406 can be formed betweenthe memory cells 412 and 412 a and the base substrate material 415. Forexample, sense amplifiers 480 and 480 a of the sensing circuitry 406 canbe formed in the base substrate material 415 such that the computecomponents 482 and 482 a without sense amplifiers 480 and 480 a arelocated above the memory array 410. Although FIG. 4 illustrates thecompute components 482 and 482 a being located above the memory array410, a portion of the compute components 482 and 482 a (e.g., the latch591 illustrated in FIG. 5) can be formed between the memory cells 412,412 a, 412 b, and 412 c, and the base substrate material 415. Thecomplementary digit lines BL-1 a and BL-2 a can be coupled to thesensing circuitry 406. As shown in FIG. 4, sensing circuitry cancomprise the sense amplifier 480 coupled to the complementary digitlines BL-1 and BL-2 via metal interconnects 468 and the sense amplifier480 a coupled to the complementary digit lines BL-1 a and BL-2 a viametal interconnects 468 a. The sense amplifiers 480 and 480 a can becoupled to compute components 482 and 482 a, respectively. The computecomponents 482 and 482 a can be a discrete collection of elements. Forexample, the compute components 482 and 482 a can comprise a pluralityof compute transistors (which can be referred to as “Boolean logic”), anaccumulator storage location, and a shift storage location. Theplurality of compute transistors can comprise a second semiconductormaterial. The second semiconductor material can be analogous to thesecond semiconductor material 264 illustrated in FIG. 2. The secondsemiconductor material can be doped to a second concentration of dopingions. As discussed above, because the plurality of compute transistorsof the sensing components are formed on and after the memory cells 412,412 a, 412 b, and 412 c, the plurality of compute transistors can beformed with a high doping concentration corresponding to fasteroperation without the concern that subsequent heating cycles will causethe doping concentration to decrease.

The transistors T1, T2, T1 a, T2 a, T1 b, T2 b, T1 c, and T2 c cancomprise a first semiconductor material. The first semiconductormaterial can be analogous to the first semiconductor material 262illustrated in FIG. 2. The first semiconductor material can be doped toa first doping concentration. The first doping concentration can be suchthat the transistors T1, T2, T1 a, T2 a, T1 b, T2 b, T1 c, and T2 c havea low leakage current. A low leakage current can improve data retentionbecause charge stored on the capacitors 438, 438 a, 438 b, and 438 cwill not leak out through the capacitors 438 and 438 a corresponding thetransistors T1, T2, T1 a, T2 a, T1 b, T2 b, T1 c, and T2 c.

The base substrate material 415 is shown to be spaced from components ofthe memory device 402 to indicate that other circuitry or components maybe between the memory cells 412, 412 a, 412 b, and 412 c and the basesubstrate material 415. For example, additional sets of memory cells412, 412 a, 412 b, and 412 c can be formed between the memory cells 412,412 a, 412 b, and 412 c illustrated in FIG. 4 and the base substratematerial 415.

In some embodiments, an axis 453 through the complementary digit linesBL-1, BL-2, BL-1 a, and BL-2 a can be considered to define a mirrorplane and the memory cells 412 b and 412 c may be considered to besubstantially mirror images of the memory cells 412 and 412 a,respectively, across the mirror plane. The term “substantially mirrorimages” is utilized to indicate that the indicated cells may be mirrorimages of one another to within reasonable tolerances of fabrication andmeasurement.

In some embodiments, the configuration of FIG. 3 can be considered tocomprise memory cells within 4F² architecture, and the configuration ofFIG. 4 can be considered to comprise memory cells within 8F²architecture.

Although not illustrated in FIG. 4, the embodiment illustrated in FIG. 4can include global metal interconnects and pads directly coupled to thesensing circuitry 406. A benefit of having the global metalinterconnects and pads directly coupled to the sensing circuitry 406 canbe reduced resistive and capacitive loads on the interface between thememory array 410 and other components of the memory device 402 (e.g.,transmitting data to and from the memory array 410). The reduction ofthe resistive and capacitive loads can be a result of the shorterdistance between the sensing circuitry 406 and the global metalinterconnects and pads. Although not illustrated in FIG. 4, the computecomponents 482 and 482 a can include selectable logical operationselection logic

A controller, such as the controller 103 illustrated in FIG. 1, can becoupled to the memory array 410 and the sensing circuitry 406, forexample, via the global metal interconnects and pads (not shown).Although not illustrated in FIG. 4, in an embodiment where senseamplifiers 480 and 480 a are located elsewhere in the memory device 402,such as being formed in the base substrate material 415, the controllercan be, for example, coupled to the memory array 410 and the computecomponents 482 and 482 a via the global metal interconnects and pads(not shown) and to the sense amplifiers 480 and 480 a via the metalinterconnects 468 and 468 a. The controller can be configured to causedata to be transmitted, via the metal interconnects 468 and 468 a,between the memory cells 412, 412 a, 412 b, and 412 c, the sensingcircuitry 406, and the global metal interconnects and pads.

The controller can be directly coupled to the global metal interconnectsand pads (not shown) such that the controller is formed over theuppermost semiconductor material of a multi-layer memory device.Minimizing the distance between the controller and the computetransistors can enhance the benefit of compute components comprising asemiconductor material having a lower concentration of doping ionsformed over a semiconductor material having a lower concentration ofdoping ions.

At least one embodiment in accordance with the present disclosure caninclude forming an array of storage elements over a base substratematerial. A semiconductor material can be formed over the array ofstorage elements. Forming the semiconductor material can compriseforming an amorphous silicon over the array of storage elements. Thesemiconductor material can be doped to a particular concentration ofdoping ions. The semiconductor material can be doped subsequent to allheating cycles associated with forming the array of storage elements.Sensing circuitry can be formed in the semiconductor material. Prior toforming the array of storage elements, a plurality of access transistorscan be formed in the base substrate material. The particularconcentration of doping ions can be higher than a concentration ofdoping ions of the base substrate material. Global metal interconnectsand pads can be formed over the sensing circuitry.

FIG. 5 is a schematic diagram illustrating sensing circuitry 506 inaccordance with a number of embodiments of the present disclosure. Thesensing circuitry 506 can be analogous to the sensing circuitry 106illustrated in FIG. 1. The sensing circuitry 506 can include a senseamplifier 580, which can be analogous to the sense amplifiers 380 and380 a illustrated in FIG. 3, and a compute component 582, which can beanalogous to the compute components 382 and 382 a illustrated in FIG. 3.The compute component 582 can comprise a plurality of computetransistors. FIG. 5 shows a sense amplifier 580 coupled to a pair ofcomplementary digit lines BL-1 and BL-2 (which can be analogous to thepair of complementary digit lines BL-1 and BL-2 and BL-1 and BL-2illustrated in FIGS. 3 and 4). The compute component 582 is coupled tothe sense amplifier 580 via pass transistors 570-1 and 570-2. The gatesof the pass transistors 570-1 and 570-2 can be controlled by a logicaloperation selection logic signal, PASS, which can be output from logicaloperation selection logic 572. FIG. 5 shows the compute component 582labeled “A” and the sense amplifier 580 labeled “B” to indicate that thedata value stored in the compute component 582 is the “A” data value andthe data value stored in the sense amplifier 580 is the “B” data valueshown in the logic tables illustrated with respect to FIG. 6.

The selectable logical operation selection logic 572 includes the swaptransistors 576, as well as logic to drive the swap transistors 576. Thelogical operation selection logic 572 includes four logic selectiontransistors: a logic selection transistor 590 coupled between the gatesof the swap transistors 576 and a TF signal control line, a logicselection transistor 592 coupled between the gates of the passtransistors 570-1 and 570-2 and a TT signal control line, a logicselection transistor 594 coupled between the gates of the passtransistors 570-1 and 570-2 and a FT signal control line, and a logicselection transistor 596 coupled between the gates of the swaptransistors 576 and a FF signal control line. Gates of the logicselection transistors 590 and 592 are coupled to the true digit lineBL-1 through isolation transistor 574-1 (having a gate coupled to an ISOsignal control line). Gates of the logic selection transistors 594 and596 are coupled to the complementary digit line BL-2 through isolationtransistor 574-2 (also having a gate coupled to an ISO signal controlline).

The plurality of compute transistors of the compute component 582 caninclude, but are not limited to, the logic selection transistors 590,592, 594, and 596. That is to say that the logic selection transistors590, 592, 594, and 596 are a subset of the plurality of computetransistors. As illustrated in FIG. 6, logic selection control signalscan be applied to the logic selection transistors 590, 592, 594, and 596to perform a particular logical operation. Thus, the logic selectiontransistors 590, 592, 594, and 596 can comprise a semiconductor material(e.g., the second semiconductor material 264 illustrated in FIG. 2),which is formed after the processing steps (e.g., heating cycles cycles)associated with forming storage elements. As a result, when thesemiconductor material is doped to a particular concentration of dopingions, the particular concentration can be maintained. The particularconcentration can be higher than that of other semiconductor materialsof an IMI device. As a result, the logic selection transistors 590, 592,594, and 596 can be doped to high concentration of doping ions such thatthe logic selection transistors 590, 592, 594, and 596 have shortswitching times corresponding to faster operation of an IMI device.

Operation of the logic selection transistors 590 and 596 are based onthe state of the TF and FF selection signals and the data values on therespective complementary digit lines at the time the ISO signal isactivated/deactivated. The logic selection transistors 590 and 596 alsooperate in a manner to control the swap transistors 576. For instance,to OPEN (e.g., turn on) the swap transistors 576, either the TF controlsignal is activated (e.g., high) with data value on the true digit lineBL-1 being “1,” or the FF control signal is activated (e.g., high) withthe data value on the complement digit line BL-2 being “1.” If eitherthe respective control signal or the data value on the correspondingdigit line (e.g., the digit line to which the gate of the particularlogic selection transistor is coupled) is not high, then the swaptransistors 576 will not be OPENed despite conduction of a particularlogic selection transistor 590 and 596.

The PASS* control signal is not necessarily complementary to the PASScontrol signal. It is possible for the PASS and PASS* control signals toboth be activated or both be deactivated at the same time. However,activation of both the PASS and PASS* control signals at the same timeshorts the pair of complementary digit lines BL-1 and BL-2 together.Logical operations results for the sensing circuitry illustrated in FIG.5 are summarized in the logic table illustrated in FIG. 6.

The sense amplifier 580 can, in conjunction with the compute component582, be operated to perform various logical operations using data froman array as an input. In a number of embodiments, the result of alogical operation can be stored back to the array without transferringthe data via a digit line address access (e.g., without firing a columndecode signal such that data is transferred to circuitry external fromthe array and sensing circuitry via local I/O lines). As such, a numberof embodiments of the present disclosure can enable performing logicaloperations and compute functions associated therewith using less powerthan various previous approaches. Additionally, since a number ofembodiments can eliminate the need to transfer data across I/O lines inorder to perform compute functions (e.g., between memory and discreteprocessor), a number of embodiments can enable an increased parallelprocessing capability as compared to previous approaches.

The sense amplifier 580 can further include equilibration circuitry,which can be configured to equilibrate the pair of complementary digitlines BL-1 and BL-2. In this example, the equilibration circuitrycomprises a transistor coupled between the pair of complementary digitlines BL-1 and BL-2. The equilibration circuitry also comprisestransistors each having a first source/drain region coupled to anequilibration voltage (e.g., VDD/2), where VDD is a supply voltageassociated with the array. A second source/drain region of a transistorcan be coupled to the digit line BL-1, and a second source/drain regionof a transistor can be coupled to the digit line BL-2. Gates of thetransistors can be coupled together, and to an equilibration (EQ)control signal line. As such, activating EQ enables the transistors,which effectively shorts the pair of complementary digit lines BL-1 andBL-2 together and to the equilibration voltage (e.g., VDD/2).

Although FIG. 5 shows sense amplifier 580 comprising the equilibrationcircuitry, embodiments are not so limited, and the equilibrationcircuitry may be implemented discretely from the sense amplifier 580,implemented in a different configuration than that shown in FIG. 5, ornot implemented at all.

As shown in FIG. 5, the compute component 582 can also comprise a latch591. The latch 591 can include a pair of cross coupled p-channeltransistors (e.g., PMOS transistors) having their respective sourcescoupled to a supply voltage (e.g., VDD). The latch 591 can include apair of cross coupled n-channel transistors (e.g., NMOS transistors)having their respective sources selectively coupled to a referencevoltage (e.g., ground), such that the latch 591 is continuously enabled.The configuration of the compute component 582 is not limited to thatshown in FIG. 5.

FIG. 6 is a logic table illustrating selectable logic operation resultsimplemented by sensing circuitry (e.g., sensing circuitry 506 shown inFIG. 5) in accordance with a number of embodiments of the presentdisclosure. The four logic selection control signals (e.g., TF, TT, FT,and FF), in conjunction with a particular data value present on thecomplementary digit lines (e.g., the pair of complementary digit linesBL-1 and BL-2 shown in FIG. 5), can be used to select one of a pluralityof logical operations to implement involving the starting data valuesstored in the sense amplifier 580 and the compute component 582. Thefour logic selection control signals (e.g., TF, TT, FT, and FF), inconjunction with a particular data value present on the complementarydigit lines (e.g., on nodes S and S*), controls the pass transistors570-1 and 570-2 and swap transistors 576, which in turn affects the datavalue in the compute component 582 and/or sense amplifier 580before/after firing. The capability to selectably control the swaptransistors 576 facilitates implementing logical operations involvinginverse data values (e.g., inverse operands and/or inverse result),among others.

Logic Table 6-1 illustrated in FIG. 6 shows the starting data valuestored in the compute component 582 shown in column A at 671, and thestarting data value stored in the sense amplifier 580 shown in column Bat 673. The other three column headings in Logic Table 6-1 refer to thestate of the pass transistors 570-1 and 570-2 and the swap transistors576, which can respectively be controlled to be OPEN or CLOSED dependingon the state of the four logic selection control signals (e.g., TF, TT,FT, and FF), in conjunction with a particular data value present on thepair of complementary digit lines BL-1 and BL-2 when the ISO controlsignal is asserted. The “NOT OPEN” column 675 corresponds to the passtransistors 570-1 and 570-2 and the swap transistors 576 both being in anon-conducting condition. The “OPEN TRUE” column 677 corresponds to thepass transistors 570-1 and 570-2 being in a conducting condition. The“OPEN INVERT” column 679 corresponds to the swap transistors 576 beingin a conducting condition. The configuration corresponding to the passtransistors 570-1 and 570-2 and the swap transistors 576 both being in aconducting condition is not reflected in Logic Table 6-1 since thisresults in the digit lines being shorted together.

Via selective control of the pass transistors 570-1 and 570-2 and theswap transistors 576, each of the three columns 675, 677, and 679 of theupper portion of Logic Table 6-1 can be combined with each of the threecolumns 675, 677, and 679 of the lower portion of Logic Table 6-1 toprovide nine (e.g., 3×3) different result combinations, corresponding tonine different logical operations, as indicated by the variousconnecting paths shown at 681. The nine different selectable logicaloperations that can be implemented by the sensing circuitry 506 aresummarized in Logic Table 6-2.

The columns of Logic Table 6-2 show a heading 683 that includes thestates of logic selection control signals (e.g., FF, FT, TF, TT). Forexample, the state of a first logic selection control signal (e.g., FF)is provided in row 684, the state of a second logic selection controlsignal (e.g., FT) is provided in row 685, the state of a third logicselection control signal (e.g., TF) is provided in row 686, and thestate of a fourth logic selection control signal (e.g., TT) is providedin row 687. The particular logical operation corresponding to theresults is summarized in row 688.

It will be understood that when an element is referred to as being “on,”“connected to” or “coupled with” another element, it can be directly on,connected, or coupled with the other element or intervening elements maybe present. In contrast, when an element is referred to as being“directly on,” “directly connected to” or “directly coupled with”another element, there are no intervening elements or layers present.

Although specific embodiments have been illustrated and describedherein, those of ordinary skill in the art will appreciate that anarrangement calculated to achieve the same results can be substitutedfor the specific embodiments shown. This disclosure is intended to coveradaptations or variations of one or more embodiments of the presentdisclosure. It is to be understood that the above description has beenmade in an illustrative fashion, and not a restrictive one. Combinationof the above embodiments, and other embodiments not specificallydescribed herein will be apparent to those of skill in the art uponreviewing the above description. The scope of the one or moreembodiments of the present disclosure includes other applications inwhich the above structures and methods are used. Therefore, the scope ofone or more embodiments of the present disclosure should be determinedwith reference to the appended claims, along with the full range ofequivalents to which such claims are entitled.

In the foregoing Detailed Description, some features are groupedtogether in a single embodiment for the purpose of streamlining thedisclosure. This method of disclosure is not to be interpreted asreflecting an intention that the disclosed embodiments of the presentdisclosure have to use more features than are expressly recited in eachclaim. Rather, as the following claims reflect, inventive subject matterlies in less than all features of a single disclosed embodiment. Thus,the following claims are hereby incorporated into the DetailedDescription, with each claim standing on its own as a separateembodiment.

What is claimed is:
 1. An apparatus, comprising: a base substratematerial; an array of memory cells formed over the base substratematerial, wherein the array includes a plurality of access transistorscomprising a first semiconductor material; and a compute componentformed over and coupled to the array, wherein the compute componentincludes a plurality of compute transistors comprising a secondsemiconductor material, wherein the second semiconductor material has ahigher concentration of doping ions than the first semiconductormaterial.
 2. The apparatus of claim 1, wherein the higher concentrationof doping ions corresponds to a higher leakage current of the pluralityof compute transistors than that of the plurality of access transistors.3. The apparatus of claim 1, wherein the higher concentration of dopingions corresponds to a shorter refresh cycle of the plurality of computetransistors than that of the plurality of access transistors.
 4. Theapparatus of claim 1, further comprising a plurality of metalinterconnects interconnecting the plurality of access transistors, thearray, and the compute component.
 5. The apparatus of claim 1, whereinthe second semiconductor material has a lower concentration of dopingions than the first semiconductor material.
 6. The apparatus of claim 1,wherein the base substrate material comprises a monocrystalline siliconbase substrate material, the first semiconductor material comprises anamorphous silicon first semiconductor material, and the secondsemiconductor material comprises an amorphous silicon secondsemiconductor material.
 7. The apparatus of claim 1, further comprisingglobal metal interconnects and pads formed on the compute component. 8.The apparatus of claim 1, further comprising sensing circuitry, whereinthe sensing circuitry comprises: the compute component; and a senseamplifier coupled to the compute component.
 9. The apparatus of claim 8,wherein the sensing circuitry is configured to perform logic operationson data stored in the array.
 10. The apparatus of claim 1, wherein thearray comprises a DRAM array.
 11. The apparatus of claim 1, wherein eachof the memory cells comprises: a first access transistor; a secondaccess transistor; and a capacitor, wherein the first and second accesstransistors comprise the first semiconductor material.
 12. The apparatusof claim 11, wherein the array of memory cells further comprises: aplurality of pairs of complementary digit lines; and a plurality ofaccess lines, wherein each of the memory cells are coupled to anassociated one of the plurality of pairs of complementary digit linesand an associated one of the plurality of access lines, and wherein thefirst and second access transistors and the capacitor are coupled inseries between the associated one of the plurality of pairs ofcomplementary digit lines with the first and second access transistorssandwiching the capacitor therebetween, and each of the first and secondaccess transistors being at a gate to the associated one of theplurality of access lines.
 13. The apparatus of claim 11, wherein thearray comprises: a first memory array tier comprising a first portion ofthe array; and a second memory array tier comprising a second portion ofthe array, wherein the second memory array tier is on the first memoryarray tier.
 14. The apparatus of claim 13, wherein the array furthercomprises: a third memory array tier comprising a third portion of thememory cells, wherein the third memory array tier is on the secondmemory array tier; and a fourth memory array tier comprising a fourthportion of the array, wherein the fourth memory array tier is on thethird memory array tier.
 15. An apparatus, comprising: a controller; amemory array coupled to the controller, comprising: a plurality ofaccess transistors formed in a monocrystalline silicon base substratematerial having a first concentration of doping ions; and an array ofstorage elements; compute component including a plurality of computetransistors comprising an amorphous silicon semiconductor materialhaving a second concentration of doping ions and coupled to the array;and a plurality of metal interconnects interconnecting, the plurality ofaccess transistors, the array, and the compute component, wherein thecompute component is formed over the array, wherein the secondconcentration is higher than the first concentration, and wherein thecontroller is configured to cause data to be transmitted, via theplurality of metal interconnects, between the plurality of accesstransistors, the array, and the compute component.
 16. The apparatus ofclaim 15, wherein the memory array further comprises a plurality ofsense amplifiers formed in the monocrystalline silicon base substratematerial, wherein the plurality of metal interconnects interconnect theplurality of access transistors, the array, the compute component, andthe plurality of sense amplifiers, and wherein the controller isconfigured to cause data to be transmitted, via the plurality of metalinterconnects, between the plurality of access transistors, the array,the compute component, and the plurality of sense amplifiers.
 17. Theapparatus of claim 15, further comprising global metal interconnects andpads formed over and coupled to the compute component, wherein thecontroller is coupled to the global metal interconnects and pads andconfigured to cause data to be transmitted to and from the array via theglobal metal interconnects and pads.
 18. The apparatus of claim 15,further comprising sensing circuitry, wherein the sensing circuitrycomprises: the compute component; and a sense amplifier coupled to thecompute component, wherein the compute component comprises: logicaloperation selection logic comprising the plurality of computetransistors, wherein logical operation selection logic controlled toperform a selected logical operation from among a plurality of logicaloperations based on one or more logic selection control signals appliedto the plurality of compute transistors, and wherein the selectedlogical operation is performed on a data value stored in at least one ofthe compute component and the sense amplifier.
 19. The apparatus ofclaim 18, wherein the logical operation selection logic is controlled toperform the selected logical operation based on a data value present ona pair of complementary digit lines.
 20. The apparatus of claim 18,wherein the sensing circuitry is configured to perform the logicaloperation without transferring data via an input/output (I/O) line. 21.A method, comprising: forming an array of storage elements over a basesubstrate material; forming a plurality of compute transistorscomprising a semiconductor material over the array; doping thesemiconductor material to a particular concentration of doping ions; andforming sensing circuitry in the semiconductor material.
 22. The methodof claim 21, wherein forming the plurality of compute transistorscomprises forming an amorphous silicon over the array.
 23. The method ofclaim 21, wherein doping the semiconductor material is subsequent to allheating cycles associated with forming the array.
 24. The method ofclaim 21, further comprising, prior to forming the array, forming aplurality of access transistors in the base substrate material, whereinthe particular concentration of doping ions is higher than aconcentration of doping ions of the base substrate material.
 25. Anapparatus, comprising: a base substrate material; an array of memorycells formed over the base substrate material, wherein the arrayincludes a plurality of access transistors comprising a firstsemiconductor material; and a compute component formed over and coupledto the array, wherein the compute component includes a plurality ofcompute transistors comprising a second semiconductor material, whereinthe second semiconductor material has a lower concentration of dopingions than the first semiconductor material.
 26. An apparatus,comprising: a base substrate material; an array of memory cells formedover the base substrate material, wherein the array includes a pluralityof access transistors comprising a first semiconductor material; and acompute component formed over and coupled to the array, wherein thecompute component includes a plurality of compute transistors comprisinga second semiconductor material, wherein the base substrate materialcomprises a monocrystalline silicon base substrate material, the firstsemiconductor material comprises an amorphous silicon firstsemiconductor material, and the second semiconductor material comprisesan amorphous silicon second semiconductor material.
 27. An apparatus,comprising: a base substrate material; an array of memory cells formedover the base substrate material, wherein the array includes a pluralityof access transistors comprising a first semiconductor material; and acompute component formed over and coupled to the array, wherein thecompute component includes a plurality of compute transistors comprisinga second semiconductor material, wherein each of the memory cellscomprises: a first access transistor; a second access transistor; and acapacitor, wherein the first and second access transistors comprise thefirst semiconductor material.
 28. An apparatus, comprising: a basesubstrate material; an array of memory cells formed over the basesubstrate material, wherein the array includes a plurality of accesstransistors comprising a first semiconductor material; a computecomponent formed over and coupled to the array, wherein the computecomponent includes a plurality of compute transistors comprising asecond semiconductor material; and global metal interconnects and padsformed on the compute component.